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MC33365 High Voltage Switching Regulator
The MC33365 is a monolithic high voltage switching regulator that is specifically designed to operate from a rectified 240 Vac line source. This integrated circuit features an on-chip 700 V/1.0 A SENSEFETt power switch, 450 V active off-line startup FET, duty cycle controlled oscillator, current limiting comparator with a programmable threshold and leading edge blanking, latching pulse width modulator for double pulse suppression, high gain error amplifier, and a trimmed internal bandgap reference. Protective features include cycle-by-cycle current limiting, input undervoltage lockout with hysteresis, bulk capacitor voltage sensing, and thermal shutdown. This device is available in a 16-lead dual-in-line package. * On-Chip 700 V, 1.0 A SENSEFET Power Switch * Rectified 240 Vac Line Source Operation * On-Chip 450 V Active Off-Line Startup FET * Latching PWM for Double Pulse Suppression * Cycle-By-Cycle Current Limiting * Input Undervoltage Lockout with Hysteresis * Bulk Capacitor Voltage Comparator * Trimmed Internal Bandgap Reference * Internal Thermal Shutdown
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16 PDIP-16 P SUFFIX CASE 648E 16 1 A WL YY WW 1 MC33365P AWLYYWW
= Assembly Location = Wafer Lot = Year = Work Week
PIN CONNECTIONS
Startup Input 1 16 Power Switch Drain
AC Input Startup Input Regulator Output 8 6 RT CT Osc 7 PWM Latch S Q PWM R Ipk Thermal LEB Compensation 9 EA 10 Voltage Feedback Input Driver BOK Startup Reg UVLO BOK 11 16 Power Switch Drain VCC 3 DC Output 1
VCC Gnd RT CT Regulator Output
3 4 5 6 7 8 (Top View) 13 12 11 10 9 Gnd BOK Voltage Feedback Input Compensation
Mirror
ORDERING INFORMATION
Device MC33365P Package PDIP-16 Shipping 25 Units/Rail
Gnd
4, 5, 12, 13
Figure 1. Simplified Application
(c) Semiconductor Components Industries, LLC, 2006
July, 2006- Rev. 4
1
Publication Order Number: MC33365/D
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1. Maximum power dissipation limits must be observed. NOTE: ESD data available upon request.
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MAXIMUM RATINGS
Storage Temperature Operating Junction Temperature Thermal Characteristics P Suffix, Dual-In-Line Case 648E Thermal Resistance, Junction-to-Air Thermal Resistance, Junction-to-Case Input Voltage Range Voltage Feedback Input (Pin 10) Compensation (Pin 9) Bulk OK Input (Pin 11) RT (Pin 6) CT (Pin 7) Power Supply Voltage (Pin 3) Startup Input Voltage (Pin 1, Note 1) Pin 3 = Gnd Pin 3 1000 F to ground Power Switch (Pin 16) Drain Voltage Drain Current Rating
ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 F, for typical values TJ = 25C, for min/max values TJ is the operating junction temperature range that applies, unless otherwise noted.)
ERROR AMPLIFIER (Pins 9, 10)
OSCILLATOR (Pin 7)
REGULATOR (Pin 8)
Output Voltage Swing High State (ISource = 100 A, VFB < 2.0 V) Low State (ISink = 100 A, VFB > 3.0 V)
Gain Bandwidth Product (f = 100 kHz, TJ = 25C)
Open Loop Voltage Gain (TJ = 25C)
Input Bias Current (VFB = 2.6 V, TJ = 0 - 125C)
Line Regulation (VCC = 20 V to 40 V, TJ = 25C)
Voltage Feedback Input Threshold
Frequency Change with Voltage (VCC = 20 V to 40 V)
Frequency CT = 390 pF TJ = 25C (VCC = 20 V) TJ = Tlow to Thigh (VCC = 20 V to 40 V) CT = 2.0 nF TJ = 25C (VCC = 20 V) TJ = Tlow to Thigh (VCC = 20 V to 40 V)
Total Output Variation over Line, Load, and Temperature
Load Regulation (IO = 0 mA to 10 mA)
Line Regulation (VCC = 20 V to 40 V)
Output Voltage (IO = 0 mA, TJ = 25C)
Characteristic
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MC33365
2 fOSC/V Symbol Regload Regline Regline GBW AVOL fOSC Vreg Vreg VFB IIB VOH VOL 0.85 2.52 Min 260 255 5.3 5.5 70 60 59 - - - - - 4.0 - Symbol RJA RJC VCC VDS IDS Tstg VIR Vin TJ 67.5 - Typ 285 - 5.3 0.2 1.0 0.6 2.6 0.1 6.5 82 20 44 30 - -55 to +150 -25 to +125 -1.0 to Vreg Value - 0.35 1.15 2.68 Max 500 310 315 200 500 5.0 2.0 8.0 7.5 94 75 76 80 15 40 400 500 700 1.0 MHz Unit kHz kHz mV mV mV dB nA V V V V V V V A C/W Unit V C C
MC33365
ELECTRICAL CHARACTERISTICS (continued) (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin
Characteristic BULK OK (Pin 11) Input Threshold Voltage Symbol Vth IIB Min 1.18 -
8 = 1.0 F, for typical values TJ = 25C, for min/max values TJ is the operating junction temperature range that applies, unless otherwise noted.)
Typ 1.25 100 -
Max 1.32 500 53
Unit V
f OSC , OSCILLATOR FREQUENCY (Hz)
CT = 100 pF
I PK, POWER SWITCH PEAK DRAIN CURRENT (A)
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Input Bias Current (VBK < Vth, TJ = 0 - 125C) nA Source Current (Turn on after VBK > Vth, TJ = 25C - 125C) Duty Cycle Maximum (VFB = 0 V) Minimum (VFB = 2.7 V) ISC 39 A % PWM COMPARATOR (Pins 7, 9) DC(max) DC(min) RDS(on) 48 - 50 0 52 0 POWER SWITCH (Pin 16) Drain-Source On-State Resistance (ID = 200 mA) TJ = 25C TJ = -25C to +125C Drain-Source Off-State Leakage Current VDS = 650 V Rise Time Fall Time - - - - - 15 - 17 39 ID(off) tr tf 0.2 50 50 100 - - A ns ns A OVERCURRENT COMPARATOR (Pin 16) Current Limit Threshold (RT = 10 k) STARTUP CONTROL (Pin 1) Ilim 0.5 0.72 0.9 Peak Startup Current (Vin = 400 V) (Note 2) VCC = 0 V VCC = (Vth(on) - 0.2 V) Istart mA - - - 2.0 2.0 40 4.0 4.0 Off-State Leakage Current (Vin = 50 V, VCC = 20 V) Startup Threshold (VCC Increasing) ID(off) 200 18 A V V UNDERVOLTAGE LOCKOUT (Pin 3) Vth(on) 11 15.2 9.5 Minimum Operating Voltage After Turn-On Power Supply Current Startup (VCC = 10 V, Pin 1 Open) Operating VCC(min) ICC 7.5 11.5 TOTAL DEVICE (Pin 3) mA - - 0.25 3.2 0.5 5.0 2. The device can only guarantee to start up at high temperature below +115C. 1.0 M 1.0 0.8 0.6 0.4 0.3 0.2 0.15 0.1 7.0 Inductor supply voltage and inductance value are adjusted so that Ipk turn-off is achieved at 5.0 s. 10 15 20 30 40 50 70 500 k C = 200 pF T 200 k CT = 500 pF 100 k CT = 1.0 nF 50 k 20 k
CT = 2.0 nF
VCC = 20 V TA = 25C
VCC = 20 V CT = 1.0 F TA = 25C
CT = 5.0 nF CT = 10 nF
10 k 7.0
10
15
20
30
50
70
RT, TIMING RESISTOR (k)
RT, TIMING RESISTOR (k)
Figure 2. Oscillator Frequency versus Timing Resistor
Figure 3. Power Switch Peak Drain Current versus Timing Resistor
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MC33365
0.8 I chg /I dscg , OSCILLATOR CHARGE/DISCHARGE CURRENT (mA) 0.5 VCC = 20 V TA = 25C Dmax, MAXIMUM OUTPUT DUTY CYCLE (%) 70 RD/RT Ratio Discharge Resistor Pin 6 to Gnd VCC = 20 V CT = 2.0 nF TA = 25C
60
0.3 0.2 0.15 0.1 0.08 7.0 10 15 20 30 50 70
50
40
30 1.0
RC/RT Ratio Charge Resistor Pin 6 to Vreg 2.0 3.0 5.0 7.0 10 TIMING RESISTOR RATIO
RT, TIMING RESISTOR (k)
Figure 4. Oscillator Charge/Discharge Current versus Timing Resistor
Figure 5. Maximum Output Duty Cycle versus Timing Resistor Ratio
, EXCESS PHASE (DEGREES)
80 Gain 60 Phase 40 20 0 -20 10
VCC = 20 V VO = 1.0 to 4.0 V RL = 5.0 M CL = 2.0 pF TA = 25C
Vsat , OUTPUT SATURATION VOLTAGE (V)
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
100
0 30 60 90 120 150 180 10 M
0 Source Saturation (Load to Ground) Vref
-1.0
- 2.0
2.0 1.0
Sink Saturation (Load to Vref) Gnd
VCC = 20 V TA = 25C
100
1.0 k
10 k
100 k
1.0 M
0
0
0.2
0.4
0.6
0.8
1.0
f, FREQUENCY (Hz)
IO, OUTPUT LOAD CURRENT (mA)
Figure 6. Error Amp Open Loop Gain and Phase versus Frequency
Figure 7. Error Amp Output Saturation Voltage versus Load Current
1.80 V
VCC = 20 V AV = -1.0 CL = 10 pF TA = 25C 20 mV/DIV
3.00 V
VCC = 20 V AV = -1.0 CL = 10 pF TA = 25C
1.75 V
1.75 V
1.70 V
0.50 V
1.0 s/DIV
1.0 s/DIV
Figure 8. Error Amplifier Small Signal Transient Response
Figure 9. Error Amplifier Large Signal Transient Response
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MC33365
V reg, REGULATOR VOLTAGE CHANGE (mV 0 I pk , PEAK STARTUP CURRENT (mA) VCC = 20 V RT = 10 k CPin 8 = 1.0 F TA = 25C 2.0 VPin 1 = 400 V TA = 25C
-20
-40
1.0
-60
Pulse tested with an on-time of 20 s to 300 s at < 1.0% duty cycle. The on-time is adjusted at Pin 1 for a maximum peak current out of Pin 3. 0 0 2.0 4.0 6.0 8.0 10 12 14
-80
0
4.0
8.0
12
16
20
Ireg, REGULATOR SOURCE CURRENT (mA)
VCC, POWER SUPPLY VOLTAGE (V)
Figure 10. Regulator Output Voltage Change versus Source Current
Figure 11. Peak Startup Current versus Power Supply Voltage
R DS(on), DRAIN-SOURCE ON-RESISTANCE ( )
32
COSS, DRAIN-SOURCE CAPACITANCE (pF)
ID = 200 mA
160 VCC = 20 V TA = 25C 120
24
16
80
8.0 Pulse tested at 5.0 ms with < 1.0% duty cycle so that TJ is as close to TA as possible. 0 -50 -25 0 25 50 75 100 125 150
40 COSS measured at 1.0 MHz with 50 mVpp. 10 100 1000 VDS, DRAIN-SOURCE VOLTAGE (V)
0 1.0
TA, AMBIENT TEMPERATURE (C)
Figure 12. Power Switch Drain-Source On-Resistance versus Temperature
Figure 13. Power Switch Drain-Source Capacitance versus Voltage
3.2 CT = 390 pF I CC, SUPPLY CURRENT (mA) 2.4 CT = 2.0 nF
100 R JA , THERMAL RESISTANCE JUNCTION-TO-AIR (C/W) L = 12.7 mm of 2.0 oz. copper. Refer to Figure 15.
1.6 RT = 10 k Pin 1 = Open Pin 4, 5, 10, 11, 12, 13 = Gnd TA = 25C 0 10 20 VCC, SUPPLY VOLTAGE (V) 30 40
10
0.8
0
1.0 0.01
0.1
1.0 t, TIME (s)
10
100
Figure 14. Supply Current versus Supply Voltage
Figure 15. P Suffix Transient Thermal Resistance
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MC33365
Printed circuit board heatsink example
80 60 40 20 PD(max) for TA = 70C RJA
L
2.0 oz Copper
4.0 3.0 2.0 1.0 0 50
L 3.0 mm Graphs represent symmetrical layout
0
0
10
20
30
40
L, LENGTH OF COPPER (mm)
Figure 16. P Suffix (DIP-16) Thermal Resistance and Maximum Power Dissipation versus P.C.B. Copper Length
PIN FUNCTION DESCRIPTION
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Pin 1
Function
Description
Startup Input
This pin connects directly to the rectified ac line voltage source. Internally Pin 1 is tied to the drain of a high voltage startup MOSFET. During startup, the MOSFET supplies internal bias, and charges an external capacitor that connects from the VCC pin to ground. This pin has been omitted for increased spacing between the rectified ac line voltage on Pin 1 and the VCC potential on Pin 3.
2 3
-
VCC
This is the positive supply voltage input. During startup, power is supplied to this input from Pin 1. When VCC reaches the UVLO upper threshold, the startup MOSFET turns off and power is supplied from an auxiliary transformer winding. These pins are the control circuit grounds. They are part of the IC lead frame and provide a thermal path from the die to the printed circuit board.
4, 5, 12, 13 6 7 8 9
Gnd RT
Resistor RT connects from this pin to ground. The value selected will program the Current Limit Comparator threshold and affect the Oscillator frequency. Capacitor CT connects from this pin to ground. The value selected, in conjunction with resistor RT, programs the Oscillator frequency. This 6.5 V output is available for biasing external circuitry. It requires an external bypass capacitor of at least 1.0 F for stability.
CT
Regulator Output Compensation
This pin is the Error Amplifier output and is made available for loop compensation. It can be used as an input to directly control the PWM Comparator. This is the inverting input of the Error Amplifier. It has a 2.6 V threshold and normally connects through a resistor divider to the converter output, or to a voltage that represents the converter output.
10
Voltage Feedback Input BOK
11
This is the non-inverting input of the bulk capacitor voltage comparator. It has an input threshold voltage of 1.25V. This pin is connected through a resistor divider to the bulk capacitor line voltage. These pins have been omitted for increased spacing between the high voltages present on the Power Switch Drain, and the ground potential on Pins 12 and 13. This pin is designed to directly drive the converter transformer and is capable of switching a maximum of 700 V and 1.0 A.
14, 15 16
-
Power Switch Drain
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P D , MAXIMUM POWER DISSIPATION (W)
100 R JA, THERMAL RESISTANCE JUNCTION-TO-AIR (C/W)
5.0
IIIII IIIII IIIII
MC33365
AC Input Startup Input Current Mirror Startup Control Band Gap Regulator 2.25 I UVLO 14.5 V/ 9.5 V 1.25 V PWM Latch S Q PWM Comparator R Leading Edge Blanking 8.1 Current Limit Comparator Compensation 405 2.6 V 10 Voltage Feedback Input 9 Error Amplifier Driver 16 Power Switch Drain 1
Regulator Output 6.5 V 8 I 6 RT
VCC 3 DC Output
BOK 11
4I Oscillator 7
CT
Thermal Shutdown
270 A Gnd 4, 5, 12, 13
Figure 17. Representative Block Diagram
Capacitor CT Compensation Oscillator Output PWM Comparator Output PWM Latch Q Output Power Switch Gate Drive Leading Edge Blanking Input (Power Switch Drain Current) Normal PWM Operating Range Output Overload
2.6 V 0.6 V
Current Limit Propagation Delay Current Limit Threshold
Figure 18. Timing Diagram
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MC33365
OPERATING DESCRIPTION
Introduction
The MC33365 represents a new higher level of integration by providing all the active high voltage power, control, and protection circuitry required for implementation of a flyback or forward converter on a single monolithic chip. This device is designed for direct operation from a rectified 240 Vac line source and requires a minimum number of external components to implement a complete converter. A description of each of the functional blocks is given below, and the representative block and timing diagrams are shown in Figures 17 and 18.
Oscillator and Current Mirror
The formula for the charge/discharge current along with the oscillator frequency are given below. The frequency formula is a first order approximation and is accurate for CT values greater than 500 pF. For smaller values of CT, refer to Figure 2. Note that resistor RT also programs the Current Limit Comparator threshold.
Ichg dscg + 5.4 RT PWM Comparator and Latch f[ Ichg dscg 4CT
The oscillator frequency is controlled by the values selected for the timing components RT and CT. Resistor RT programs the oscillator charge/discharge current via the Current Mirror 4 I output, Figure 4. Capacitor CT is charged and discharged by an equal magnitude internal current source and sink. This generates a symmetrical 50 percent duty cycle waveform at Pin 7, with a peak and valley threshold of 2.6 V and 0.6 V respectively. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the inverting input of the AND gate Driver high. This causes the Power Switch gate drive to be held in a low state, thus producing a well controlled amount of output deadtime. The amount of deadtime is relatively constant with respect to the oscillator frequency when operating below 1.0 MHz. The maximum Power Switch duty cycle at Pin 16 can be modified from the internal 50% limit by providing an additional charge or discharge current path to CT, Figure 19. In order to increase the maximum duty cycle, a discharge current resistor RD is connected from Pin 7 to ground. To decrease the maximum duty cycle, a charge current resistor RC is connected from Pin 7 to the Regulator Output. Figure 5 shows an obtainable range of maximum output duty cycle versus the ratio of either RC or RD with respect to RT.
Current Mirror 2.25 I I RC RT 4I CT 7 Oscillator Blanking Pulse 6 Current Limit Reference
The pulse width modulator consists of a comparator with the oscillator ramp voltage applied to the non-inverting input, while the error amplifier output is applied into the inverting input. The Oscillator applies a set pulse to the PWM Latch while CT is discharging, and upon reaching the valley voltage, Power Switch conduction is initiated. When CT charges to a voltage that exceeds the error amplifier output, the PWM Latch is reset, thus terminating Power Switch conduction for the duration of the oscillator ramp-up period. This PWM Comparator/Latch combination prevents multiple output pulses during a given oscillator clock cycle. The timing diagram shown in Figure 18 illustrates the Power Switch duty cycle behavior versus the Compensation voltage.
Current Limit Comparator and Power Switch
Regulator Output 1.0 8
RD
The MC33365 uses cycle-by-cycle current limiting as a means of protecting the output power switch from overstress. Each on-cycle is treated as a separate situation. Current limiting is implemented by monitoring the output switch current buildup during conduction, and upon sensing an overcurrent condition, immediately turning off the switch for the duration of the oscillator ramp-up period. The Power Switch is constructed as a SENSEFET allowing a virtually lossless method of monitoring the drain current. It consists of a total of 1462 cells, of which 36 are connected to a 8.1 ground-referenced sense resistor. The Current Sense Comparator detects if the voltage across the sense resistor exceeds the reference level that is present at the inverting input. If exceeded, the comparator quickly resets the PWM Latch, thus protecting the Power Switch. The current limit reference level is generated by the 2.25 I output of the Current Mirror. This current causes a reference voltage to appear across the 405 resistor. This voltage level, as well as the Oscillator charge/discharge current are both set by resistor RT. Therefore when selecting the values for RT and CT, RT must be chosen first to set the Power Switch peak drain current, while CT is chosen second to set the desired Oscillator frequency. A graph of the Power Switch peak drain current versus RT is shown in Figure 3 with the related formula below.
I pk + 8.8 R T - 1.077 1000
PWM Comparator
Figure 19. Maximum Duty Cycle Modification
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MC33365
The Power Switch is designed to directly drive the converter transformer and is capable of switching a maximum of 700 V and 1.0 A. Proper device voltage snubbing and heatsinking are required for reliable operation. A Leading Edge Blanking circuit was placed in the current sensing signal path. This circuit prevents a premature reset of the PWM Latch. The premature reset is generated each time the Power Switch is driven into conduction. It appears as a narrow voltage spike across the current sense resistor, and is due to the MOSFET gate to source capacitance, transformer interwinding capacitance, and output rectifier recovery time. The Leading Edge Blanking circuit has a dynamic behavior in that it masks the current signal until the Power Switch turn-on transition is completed. The current limit propagation delay time is typically 262 ns. This time is measured from when an overcurrent appears at the Power Switch drain, to the beginning of turn-off.
Error Amplifier
VBULK Vref
RUpper
BOK 11 RLower
50 mA 1.25 V Protection Logic
Figure 20. Bulk OK Functional Operation Undervoltage Lockout
An fully compensated Error Amplifier with access to the inverting input and output is provided for primary side voltage sensing, Figure 17. It features a typical dc voltage gain of 82 dB, and a unity gain bandwidth of 1.0 MHz with 78 degrees of phase margin, Figure 6. The noninverting input is internally biased at 2.6 V 3.1% and is not pinned out. The Error Amplifier output is pinned out for external loop compensation and as a means for directly driving the PWM Comparator. The output was designed with a limited sink current capability of 270 A, allowing it to be easily overridden with a pull-up resistor. This is desirable in applications that require secondary side voltage sensing.
Bulk Capacitor Voltage Comparator
An Undervoltage Lockout comparator has been incorporated to guarantee that the integrated circuit has sufficient voltage to be fully functional before the output stage is enabled. The UVLO comparator monitors the VCC voltage at Pin 3 and when it exceeds 14.5 V, the reset signal is removed from the PWM Latch allowing operation of the Power Switch. To prevent erratic switching as the threshold is crossed, 5.0 V of hysteresis is provided.
Startup Control
In order to avoid output voltage bouncing during electricity brownout condition, a Bulk Capacitor Voltage Comparator with programmable hysteresis is included in this device. The non-inverting input, pin 11, is connected to the voltage divider comprised of RUpper and RLower as shown in Figure 20 monitoring the bulk capacitor voltage level. The inverting input is connected to a threshold voltage of 1.25 V internally. As bulk capacitor voltage drops below the pre-programmed level, (Pin 11 drops below 1.25 V), a reset signal will be generated via internal protection logic to the PWM Latch so turning off the Power Switch immediately. An internal current source controlled by the state of the comparator provides a means to program the voltage hysteresis. The following equation shows the relationship between VBULK levels and the voltage divider network resistors.
RUpper + 20 RLower + 25 [ VBulk_H * VBulk_L ] [ VBulk_H * VBulk_L ] VBulk_H * 1.25 in K Ohm in K Ohm
An internal Startup Control circuit with a high voltage enhancement mode MOSFET is included within the MC33365. This circuitry allows for increased converter efficiency by eliminating the external startup resistor, and its associated power dissipation, commonly used in most off-line converters that utilize a UC3842 type of controller. Rectified ac line voltage is applied to the Startup Input, Pin 1. This causes the MOSFET to enhance and supply internal bias as well as charge current to the VCC bypass capacitor that connects from Pin 3 to ground. When VCC reaches the UVLO upper threshold of 15.2 V, the IC commences operation and the startup MOSFET is turned off. Operating bias is now derived from the auxiliary transformer winding, and all of the device power is efficiently converted down from the rectified ac line. The startup MOSFET will provide a steady current of 1.7 mA, Figure 11, as VCC increases or shorted to ground. The startup MOSFET is rated at a maximum of 400 V with VCC shorted to ground, and 500 V when charging a VCC capacitor of 1000 F or less.
Regulator
A low current 6.5 V regulated output is available for biasing the Error Amplifier and any additional control system circuitry. It is capable of up to 10 mA and has
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MC33365
short-circuit protection. This output requires an external bypass capacitor of at least 1.0 F for stability.
Thermal Shutdown and Package
Internal thermal circuitry is provided to protect the Power Switch in the event that the maximum junction temperature is exceeded. When activated, typically at 150C, the Latch is forced into a `reset' state, disabling the Power Switch. The Latch is allowed to `set' when the Power Switch temperature falls below 140C. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a substitute for proper heatsinking.
The MC33365 is contained in a heatsinkable plastic dual-in-line package in which the die is mounted on a special heat tab copper alloy lead frame. This tab consists of the four center ground pins that are specifically designed to improve thermal conduction from the die to the circuit board. Figure 16 shows a simple and effective method of utilizing the printed circuit board medium as a heat dissipater by soldering these pins to an adequate area of copper foil. This permits the use of standard layout and mounting practices while having the ability to halve the junction to air thermal resistance. The examples are for a symmetrical layout on a single-sided board with two ounce per square foot of copper.
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MC33365
PACKAGE DIMENSIONS
PDIP-16 P SUFFIX CASE 648E-01 ISSUE O
-A- R
16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION A AND B DOES NOT INCLUDE MOLD PROTRUSION. 5. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.25 (0.010). 6. ROUNDED CORNER OPTIONAL. DIM A B C D F G H J K L M P R S INCHES MIN MAX 0.740 0.760 0.245 0.260 0.145 0.175 0.015 0.021 0.050 0.070 0.100 BSC 0.050 BSC 0.008 0.015 0.120 0.140 0.295 0.305 0_ 10 _ 0.200 BSC 0.300 BSC 0.015 0.035 MILLIMETERS MIN MAX 18.80 19.30 6.23 6.60 3.69 4.44 0.39 0.53 1.27 1.77 2.54 BSC 1.27 BSC 0.21 0.38 3.05 3.55 7.50 7.74 0_ 10 _ 5.08 BSC 7.62 BSC 0.39 0.88
M -B- L
1
8
P
F
J
C S G H D 13 PL 0.25 (0.010)
M
-T-
SEATING PLANE
K
TB
S
A
S
The product described herein (MC33365), may be covered by one or more of the following U.S. patents: 4,553,084; 5,418,410; 5,477,175. There may be other patents pending. SENSEFET is a trademark of Semiconductor Components Industries, LLC (SCILLC)
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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MC33365/D

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